PURPOSE: To achieve a reduction in the cost, by supplying a clock pulse to a functioning circuit from a test terminal once prohibiting an input thereto from a preceding frequency dividing stage.

CONSTITUTION: A frequency dividing stage 3 and a driving circuit 4 composes a functioning circuit to be tested. Normally, with a test terminal 6 held at '0', a frequency dividing stage 2 starts, an output thereof is inverted in the level through a gate circuit 5 and supplied to a frequency dividing stage 3 to generate a pulse for driving a motor from a circuit 4 receiving the output from the frequency dividing stage 3. When carrying out a test, a testing clock pulse is supplied to the terminal 6 with the pulse width at the '0' level being smaller than a half that of the output from the preceding frequency dividing stage 2. The frequency dividing stage 2 is reset by '1' level of the clock pulse. On the other hand, the clock pulse is inverted in the level with the circuit 5 and fed to the frequency dividing stage 3 to perform a frequency dividing operation and an output pulse is generated from the circuit 4 according to the output pulse thereof. Thus, the frequency dividing stage 3 and the circuit 4 are tested.