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Patent Searching and Data


Title:
INTEGRATED CIRCUIT WITH TESTING FUNCTION
Document Type and Number:
Japanese Patent JPS638587
Kind Code:
A
Abstract:

PURPOSE: To achieve a testing of a function circuit without use of a special test terminal, by supplying a clock pulse for testing to an alarm terminal to reset a desired frequency dividing stage while a clock pulse is supplied to the function circuit.

CONSTITUTION: When testing a function circuit, first, an alarm terminal 6 normally set to '0' is set to '1' and then, a clock pulse is supplied thereto. When pulse from an output Q3 of a frequency dividing stage 3 does not fall with at the pulse state at 0, outputs Q and -Q of an FF circuit 7 are held at 1 and 0 respectively to generate an alarm signal from an alarm control circuit 5 while a clock pulse passes through a gage circuit 9. Then, a clock pulse passes through a gate circuit 10 to reset a frequency dividing stage 2 while passing through a gate circuit 11 to be supplied to the frequency dividing stage 3. Thus, a driving circuit 4 is tested, too.


Inventors:
ISHITA YUUJI
Application Number:
JP15301786A
Publication Date:
January 14, 1988
Filing Date:
June 30, 1986
Export Citation:
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Assignee:
SEIKOSHA KK
International Classes:
G04D7/00; G04C21/02; G04G3/02; (IPC1-7): G04D7/00; G04G3/02
Domestic Patent References:
JPS58154688A1983-09-14
JPS57201885A1982-12-10
Attorney, Agent or Firm:
Kazuko Matsuda