Title:
集積回路
Document Type and Number:
Japanese Patent JP6592124
Kind Code:
B2
Abstract:
In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.
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Inventors:
Kiyoshi Kato
Application Number:
JP2018020824A
Publication Date:
October 16, 2019
Filing Date:
February 08, 2018
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H03K19/096; H01L21/8234; H01L27/088; H01L29/786
Domestic Patent References:
| JP5276016A | ||||
| JP63066789A | ||||
| JP2011086929A | ||||
| JP2009004733A | ||||
| JP5074155A | ||||
| JP9232942A |
Other References:
富沢 孝 監訳,「CMOS VLSI設計の原理」,日本,丸善株式会社,1988年 8月30日,pp.138-141, 181-182