Title:
INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH01155661
Kind Code:
A
Abstract:
PURPOSE:To reduce the collector saturation resistance of a low breakdown strength transistor to an arbitrary value by a method wherein an N<+> type protrusion is built in the low breakdown strength transistor collector layer. CONSTITUTION:An anode film 2 is formed on an Si substrate 1, an opening 3 is provided in the oxide film 2 for isolation, when another opening 10 with its width (w) smaller than the width W of the oxide film 2. In an anisotropic etching process to follow, a shallow V-shaped groove 11 with its depth (d)=(W /2)tan54.7 deg. is formed in the opening 10. The oxide film 2 is removed, an N<+> diffusion layer 4 is formed, an isolating oxide film 5 is formed, a supporting polycrystalline layer 6 is formed, and the Si substrate 1 is polished as deep as the A-A' level. In this process, the N<+> layer in the shallow V-shaped groove 11 is converted into an N<+> type protrusion 12 protruding in an isolated island 1 by the depth (d) that is the depth of the V-shaped groove 11. Finally, on a dielectric isolating substrate, bases 7 and 7', emitters 8 and 8', and collectors 9 and 9' are constructed.
Inventors:
TSUCHIYA YOSHIMI
Application Number:
JP31445087A
Publication Date:
June 19, 1989
Filing Date:
December 11, 1987
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/762; H01L21/331; H01L21/76; H01L21/8222; H01L27/06; H01L29/72; H01L29/73; H01L29/732; (IPC1-7): H01L21/76; H01L27/06; H01L29/72
Attorney, Agent or Firm:
Masuo Oiwa (2 outside)