PURPOSE: To output data on an address where a transmission error occurs and data to the outside if the transfer error occurs between a microprocessor and a memory, and to set whether or not access is attained again and its frequency at the time of the transfer error.
CONSTITUTION: When previously set saving conditions are met, an operand management circuit 11 saves address data, stored in an address buffer 9, in a working register 12 and then saving address data of an operand are generated by controlling an operand address generating circuit 8 to save the operand, stored in a data buffer 10, in a memory 3; and the address data stored in the working register 12 are transferred to the data buffer 10 and then saving address for the address data is generated by controlling the address generating circuit 9 to saves the object address data in the memory 3.
JP2013196644 | STORAGE DEVICE, AND CONTROL METHOD FOR THE SAME |
JP5563125 | Memory access device |
OHASHI KAZUHIKO
TOSHIBA MICRO ELECTRONICS
Next Patent: MEMORY TEST SYSTEM