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Title:
INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH06202964
Kind Code:
A
Abstract:

PURPOSE: To output data on an address where a transmission error occurs and data to the outside if the transfer error occurs between a microprocessor and a memory, and to set whether or not access is attained again and its frequency at the time of the transfer error.

CONSTITUTION: When previously set saving conditions are met, an operand management circuit 11 saves address data, stored in an address buffer 9, in a working register 12 and then saving address data of an operand are generated by controlling an operand address generating circuit 8 to save the operand, stored in a data buffer 10, in a memory 3; and the address data stored in the working register 12 are transferred to the data buffer 10 and then saving address for the address data is generated by controlling the address generating circuit 9 to saves the object address data in the memory 3.


Inventors:
KOMIYAJI KAZUHIDE
OHASHI KAZUHIKO
Application Number:
JP2093A
Publication Date:
July 22, 1994
Filing Date:
January 04, 1993
Export Citation:
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Assignee:
TOSHIBA CORP
TOSHIBA MICRO ELECTRONICS
International Classes:
G06F12/16; H01J37/28; H01L21/66; G01R31/302; (IPC1-7): G06F12/16; G01R31/302; H01J37/28; H01L21/66
Attorney, Agent or Firm:
Hidekazu Miyoshi (1 outside)