To provide an integrated circuit with a built-in data processing element, for which it is not necessary to increase the number of input terminals even when the number of input nodes is increased, by providing an input terminal, a shift register and plural processing blocks at a neural network.

The time sequential data of three bits inputted to an input terminal IN1 of a data processing element A are given to the D input terminal of a D flip-flop D1. Then, the element A performs similar processing at a conventional data processing element, an intermediate layer node and an output layer node. Thus is similar even in the case of time sequential data x(t), x(t-1),..., x(t-n) of n+1 bits and at the (n+1)th block from the input of data x(t), the processing result to be found is outputted. Therefore, when using the time sequential data x(t), x(t-1),..., x(t-n) of n+1 bits as the input data of the data processing element, by incorporating the shift register composed of (n+1) pieces of D flip-flops, one input terminal is enough for the data processing element.