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Title:
INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH118550
Kind Code:
A
Abstract:

To provide a frequency divider with which a frequency dividing ratio of an arbitrary multiple of '2' can be provided and only a noise having the only double frequency of the frequency of an input signal is generated irrespective of the frequency-dividing ratio provided.

A frequency divider DIV/4 is composed of memory cells DL1-DL4 formed by emitter coupling logic(ECL) techniques, and a loop is composed of the data passage of these memory cells DL1-DL4 but a data output terminal Q4 of the final memory cell DL4 is cross connected to a data input terminal D1 of the 1st memory cell DL1. The clock input terminals of odd- numbered memory cells DL1 and DL3 are connected to an input terminal IN of the frequency divider DIV/4, and the clock input terminals of the other memory cells DL2 and DL4 are cross connected to this input terminal IN of this frequency divider DIV/4.


Inventors:
CANARD DAVID
FILLATRE VINCENT
Application Number:
JP10471798A
Publication Date:
January 12, 1999
Filing Date:
April 15, 1998
Export Citation:
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Assignee:
KONINKL PHILIPS ELECTRONICS NV
International Classes:
H03L7/183; H03J5/02; H03K3/286; H03K23/54; H03K23/64; H04B1/26; (IPC1-7): H03K23/64; H03K3/286; H03L7/183; H04B1/26
Attorney, Agent or Firm:
杉村 暁秀 (外5名)



 
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