To provide a frequency divider with which a frequency dividing ratio of an arbitrary multiple of '2' can be provided and only a noise having the only double frequency of the frequency of an input signal is generated irrespective of the frequency-dividing ratio provided.
A frequency divider DIV/4 is composed of memory cells DL1-DL4 formed by emitter coupling logic(ECL) techniques, and a loop is composed of the data passage of these memory cells DL1-DL4 but a data output terminal Q4 of the final memory cell DL4 is cross connected to a data input terminal D1 of the 1st memory cell DL1. The clock input terminals of odd- numbered memory cells DL1 and DL3 are connected to an input terminal IN of the frequency divider DIV/4, and the clock input terminals of the other memory cells DL2 and DL4 are cross connected to this input terminal IN of this frequency divider DIV/4.
JP2010119073 | DIVIDER CIRCUITRY |
JPS5294710 | RECEIVER |
JPS5753157 | OSCILLATION FREQUENCY CONTROL SYSTEM DUE TO KEYBOARD |
FILLATRE VINCENT