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Title:
INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5793722
Kind Code:
A
Abstract:

PURPOSE: To increase the noise margin of an input signal, by using a static type comparator as an input circuit and applying an input signal to one input terminal and a reference voltage generated in an integrated circuit to another input terminal.

CONSTITUTION: When an input signal is at "1" level, the source of an MOSFETT1 is at Vc potential, and an MOSFETT4 turns on and a T3 turns off. When the input signal changes from "1" to "0" level, the FETT4 turns off and the T3 turns on through the difference of conductive resistance of the MOSFETs T1, T2, and the output optential is at "1" level. Inversely, when the input signal changes from "0" to "1" level, the FETT3 inverts off and the T4 inverts on through the difference of conductor resistance of the FETs T1, T2 and the output potential is at "0" level. Specified noise margin can be obtained by the hysteresis characteristics of a comparator 10.


Inventors:
IWAHASHI HIROSHI
ASANO MASAMICHI
Application Number:
JP17052180A
Publication Date:
June 10, 1982
Filing Date:
December 03, 1980
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H03K19/0185; H03K5/08; H03K5/1252; H03K17/30; (IPC1-7): H03K5/01; H03K17/30; H03K19/00
Domestic Patent References:
JPS5520054A1980-02-13