To provide a technique for reducing the queue time (latency) of a semiconductor device going through a manufacturing process.

An integrated tool and a method for reducing the defects when manufacturing a semiconductor device, by reducing the queue time during the period of manufacturing process, are provided. The integrated tool may include at least one polishing tool having at least one polishing module, and at least one deposition tool having at least one deposition chamber. At least one pump down chamber may connect the polishing tool with the deposition tool. The at least one pump down chamber includes a passage through which the semiconductor device is passed. Defects in the semiconductor device are reduced by reducing the queue time in various stages of a manufacturing process.