Title:
INTEGRATOR AND INTEGRATING METHOD
Document Type and Number:
Japanese Patent JP3901811
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To grasp accurate integrated traveling distance.
SOLUTION: In the case where an integration value which is stored in a nonvolatile storage device in processes from a step ST4 to a step ST8 is in the range from 0 to 999,999, an operation processing part sets the display data to be the same value as the integration value. In the case that an integration value is in the range from 1,000,000 to 1,999,998, the operation processing part sets the display data to be a value obtained by substituting 1,000,000 from the integration value. In the case that an integration value is at least 1,999,999, the operation processing part sets the display data to be 999,999 (km). In a step 9, the value of the display data is displayed as the integrated traveling distance.
Inventors:
Masakazu Kobayashi
Yoshito Nakamura
Yoshito Nakamura
Application Number:
JP28238497A
Publication Date:
April 04, 2007
Filing Date:
October 15, 1997
Export Citation:
Assignee:
Calsonic Kansei Co., Ltd.
Toshiba Microelectronics Co., Ltd.
Toshiba Corporation
Toshiba Microelectronics Co., Ltd.
Toshiba Corporation
International Classes:
G01C22/00; G01C22/02; (IPC1-7): G01C22/00
Domestic Patent References:
| JP7218283A | ||||
| JP5231874A | ||||
| JP6249674A |
Attorney, Agent or Firm:
Hiroaki Tazawa
Konobu Kato
Konobu Kato
Previous Patent: FREQUENCY SYNTHESIZER WITH CORRECTION CIRCUIT
Next Patent: TRAVELING DISTANCE ALARM SYSTEM
Next Patent: TRAVELING DISTANCE ALARM SYSTEM