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Patent Searching and Data


Title:
INTER-CARRIER DELAY ADJUSTMENT CIRCUIT
Document Type and Number:
Japanese Patent JPH07193611
Kind Code:
A
Abstract:

PURPOSE: To obtain the delay time adjustment circuit transmitting correctly a data signal string of other carrier even when an error takes place in any carrier when the data signal string of STM-N frame configuration on which plural pointers and plural sets of real information are multiplied by using the multi-carrier digital radio transmission system.

CONSTITUTION: A fixed delay circuit 14 corresponding to a specific Carrier 1, selection circuits 15, 16 corresponding respectively to other carriers 2, 3 and fixed delay circuits 17, 18 are used to generate reference clocks 221, 222, 223 and reference frame pulses 321, 322, 323. The selection circuit is controlled by a pointer discrimination section 13 based on a pointer detected by a pointer detection circuit 12 and selectively provides any of a reception clock 201 obtained from the specific carrier, an output frame pulse 301, reception clocks 202, 203 obtained from each carrier and output frame pulses 302, 303.


Inventors:
MUTO HIDEYUKI
Application Number:
JP33038693A
Publication Date:
July 28, 1995
Filing Date:
December 27, 1993
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04L27/38; H04J3/00; H04J4/00; H04L7/00; (IPC1-7): H04L27/38; H04J3/00; H04J4/00
Attorney, Agent or Firm:
Yosuke Goto (2 outside)