Title:
INTER-CIRCUIT BLOCK INTERFACE DEVICE
Document Type and Number:
Japanese Patent JPH08331122
Kind Code:
A
Abstract:
PURPOSE: To speed up the processing of a control signal from a CPU to perform the input/output control, the storage/readout in/from buffer memory and distribution/concentration to plural input/output circuits, etc., of an ATM multiplex signal.
CONSTITUTION: An interface 9 in which an entry sequence output memory device is arranged is provided between a central processing control unit 8 and a control circuit 6, and the control signal of the central processing control unit 8 is stored transiently in the entry sequence output memory device, and the control signal stored in the entry sequence output memory device is sent out to the control circuit 6 corresponding to the processing speed of the control circuit 6.
Inventors:
SHIMURA MASARU
Application Number:
JP15517295A
Publication Date:
December 13, 1996
Filing Date:
May 30, 1995
Export Citation:
Assignee:
TOKYO DENSHI SEKKEI KK
International Classes:
H04Q3/00; H04L12/02; H04L12/28; (IPC1-7): H04L12/02; H04L12/28; H04Q3/00