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Title:
INTER-MAIN STORAGE DEVICE DATA TRANSFER PROCESSING MECHANISM
Document Type and Number:
Japanese Patent JPH096714
Kind Code:
A
Abstract:

PURPOSE: To execute data transfer between main storage devices without increasing hardware quantity and complicating hardware concerning an information processing system having a CPU, I/O processor and main storage device.

CONSTITUTION: When an inter-main memory data transfer request is issued, a main storage device 300 receives this request from a system bus 500 to an address command register 421, and transfer data are passed through an address command buffer 422 and read from a main memory 302. These data are held in a read data register 411 together with a write address from an adder 436 and a write command from a command generating circuit 437, sent to a read data buffer 421 and issued to the system bus 500 as a write request. This write request is received by the same or different main storage device and written in the main memory by a write data register 401 and a write data buffer.


Inventors:
MIZUKAMI SHINYA
Application Number:
JP15472095A
Publication Date:
January 10, 1997
Filing Date:
June 21, 1995
Export Citation:
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Assignee:
KOFU NIPPON DENKI KK
International Classes:
G06F12/02; G06F13/28; G06F15/16; G06F15/163; G06F15/177; (IPC1-7): G06F13/28; G06F12/02
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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