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Title:
INTER-PROCESSOR COMMUNICATION SYSTEM
Document Type and Number:
Japanese Patent JPH0581211
Kind Code:
A
Abstract:

PURPOSE: To make it possible to transfer data between plural CPU boards without preparing a specific program on the transferred side so as to minimize a bus locking period.

CONSTITUTION: In the case of transferring a program or data stored in a RAM 12 to a CPU board 2, a CPU 11 in a CPU board 1 locks an external bus 3 only for the execution period of a TEST-AND-SET instruction, obtains the lock state based upon lock information allocated to a part of an address space in itself and stored in a bidirectional memory 23, writes the program or the like in the memory 23, and then changes the lock information to a non-locked state. A CPU 21 in the CPU board 2 accesses the program or data allocated to a part of its address space and transferred to the memory 23 so as to exclude access competition with the other CPU 11 based upon the TEST-AND-SET instruction to execute the program or utilize the data.


Inventors:
SHIMOJIMA TAKEHIKO
MIYAUCHI TETSUO
Application Number:
JP26894891A
Publication Date:
April 02, 1993
Filing Date:
September 20, 1991
Export Citation:
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Assignee:
NEC CORP
NIPPON DENKI MICOM TECH KK
International Classes:
G06F12/00; G06F15/16; G06F15/167; G06F15/173; G06F15/177; (IPC1-7): G06F12/00; G06F15/16
Attorney, Agent or Firm:
Sakai Hiromi