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Title:
INTERACTIVE BLOCK ARRANGEMENT CORRECTION SYSTEM
Document Type and Number:
Japanese Patent JPH06124320
Kind Code:
A
Abstract:

PURPOSE: To prevent a local nonwiring state by easily correcting the arrangement of blocks for equalizing the congestion of wiring.

CONSTITUTION: This system is provided with an information input means 2 which reads arrangement information and logical connection information on blocks, a virtual wiring map generating means 3 which generates a map for storing virtual wiring paths, a virtual wiring means 4 for virtual wiring, and a congestion calculating and displaying means 5 which registers information on connection relation in coordinates of the map, calculates the congestion of wiring, and displaying a color corresponding to the level. Further, this system consists of an area specifying means 6 which specifies an area of virtual wiring to be improved, a connection relation and display means 7 which detects and displays the connection relation registered in the coordinates and blocks connected in the connection relation, an interactive arrangement correcting means 8 which corrects the arrangement interactively over a look at the overall congestion of wiring, and an arrangement congestion check means 9 which checks whether or not the maximum value of the wiring congestion after the arrangement correction exceeds the maximum value before the arrangement correction.


Inventors:
KUROKI KANA
Application Number:
JP12842792A
Publication Date:
May 06, 1994
Filing Date:
May 21, 1992
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L21/82; G06F17/50; H05K3/00; (IPC1-7): G06F15/60; H01L21/82; H05K3/00
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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