To provide a method for interconnecting a ground line, a signal line and a power line inside a semiconductor chip carrier.

This method is provided with a step for forming a plurality of insulating layers having conductor lines including power lines 38A and 38C and ground lines 38B and 38D parallel arrayed inside one plane. The parallel lines are orthogonally oriented between two insulating layers among a plurality of insulating layers. Between the planes, via connection parts 40A, 40B, 40C and 40D are formed for connecting the power lines 38A and 38C in one plane to the other power lines 36D and 36B in the other plane. Between the planes, via connection parts 42A, 42B, 42C and 42D are formed for connecting the ground lines 38B and 38D in a first plane to other ground lines 36C and 36A in a second plane. The signal lines are formed parallel between the ground lines and the power lines.