Title:
容量性負荷の作動のためのインターフェース回路
Document Type and Number:
Japanese Patent JP4518475
Kind Code:
B2
Abstract:
The transistors (T1,T2) are provided to short-circuit the input of a load when a main supply voltage to the input of the load is not effected.
Inventors:
Claus fisher
Josef Cray Meier
Josef Cray Meier
Application Number:
JP2004098712A
Publication Date:
August 04, 2010
Filing Date:
March 30, 2004
Export Citation:
Assignee:
Patent-Treuhand-Gesellschaft fuer elektrische Gluehlampen mbH
International Classes:
H05B41/282; H05B41/392; H03K17/60; H05B41/232; H05B41/285; H05B41/288
Domestic Patent References:
| JP2001319798A |
Attorney, Agent or Firm:
Toshio Yano
Toshiomi Yamazaki
Takuya Kuno
Einzel Felix-Reinhard
Reinhard Einsel
Toshiomi Yamazaki
Takuya Kuno
Einzel Felix-Reinhard
Reinhard Einsel