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Title:
INTERFACE CIRCUIT BETWEEN FRAME RELAY AND ATM
Document Type and Number:
Japanese Patent JP3046289
Kind Code:
B
Abstract:

PROBLEM TO BE SOLVED: To relieve a load imposed on a traffic control processor by connecting the traffic control processor to a CPU bus, separating it from a PCI bus and connecting the traffic control processor to the PCI bus via a bridge.
SOLUTION: A PCI bus 204 and a CPU bus 209 provided to an interface circuit are separated for data transmission by a bridge 205, then the buses are used simultaneously. Since the interface circuit 200 adopts a double bus structure, collision between data transmission reception to/from a payload memory 202 and a bus cycle of the traffic control processor 207 is prevented. An HDLC interface 201 sends/receives a data frame (frame relay I/O) to/from a frame relay backbone network and an SAR interface 203 sends/receives an ATM data cell (ATM cell I/O) to/from an ATM backbone network. The interface circuit 200 maintains a larger burst even for a short data frame.


Inventors:
Michelle, Von Arnen J.
Sreejis, Sreedharan
Application Number:
JP1999000000186
Publication Date:
March 17, 2000
Filing Date:
January 04, 1999
Export Citation:
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Assignee:
SAMSUNG ELECTRONICS CO LTD
International Classes:
H04L12/66; H04L12/56; H04Q11/04; (IPC1-7): H04L12/66; H04L12/28



 
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