To provide an interface circuit for a bus SW capable of preventing the occurrence of errors in the data of all interface panels even when a buffer fails.

In the respective interface panels 1, parallel data from a TSW circuit 3 are sent out to a P/S circuit 6 corresponding to one bus line selected by an MPU. The P/S circuit 6 converts the inputted parallel data to serial data and sends them out to an output buffer 4 and the output buffer 6 amplifies the inputted serial data and sends them out to one selected bus.