PURPOSE: To prevent a latch miss from being generated by passing a data signal during the low-level period of a clock signal and temporarily holding the data signal in rising to a high level by a second memory cell group.
CONSTITUTION: The interface circuit is provided with a buffer 8 for the clock signal to be led into a clock signal terminal 7, and a buffer 3 for the data signal to be led into a data signal terminal 2 and timing signal distributing means 10-13 to hierarchically distribute the clock signals, and a first memory cell group 5 to store the data signal according to the clock signal, which is distributed by the distributing means 10-13, at the first timing and to execute digital processing. Further, the second memory cell group 4 is provided to be connected respectively between the data buffer 3 and a first memory cell group 5, to temporarily hold the data signal from the data buffer 3 according to the clock signal 14 at a second timing, which is earlier than the first timing in a phase, and to deliver the data to the first memory cell 5. Thus, a data proba bility period can be prolonged to the first memory cell group in the next step and the mis latch can be prevented.
YAMADA MASAHIRO
TOKORO KENICHI
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