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Title:
INTERFACE CIRCUIT
Document Type and Number:
Japanese Patent JPH0292024
Kind Code:
A
Abstract:

PURPOSE: To reduce the circuit scale by storing a specific data tc each flip-flop of a shift register, inputting a serial clock signal and a serial data, shifting them and detecting whether a prescribed bit number of the serial data is inputted or not.

CONSTITUTION: A shift register 2 latches a specific data from a specific data generating circuit 1 to flip-flops FF1-FFn and shifts the specific data and a serial data DT1 sequentially. A detection circuit 3 inputs a data outputted serially from the shift register 2. Whether or not the data DT1 of a prescribed bit number is inputted from the specific data included in the serial data is detected and a read end signal RE is outputted when the data of a prescribed bit number is inputted. Since the input bit number of the serial data is implemented by a simple specific data generating circuit and a detection circuit, the circuit scale is reduced.


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Inventors:
SAKURAI HIROFUMI
AKIYAMA KAZUHIRO
Application Number:
JP24500788A
Publication Date:
March 30, 1990
Filing Date:
September 28, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03M9/00; (IPC1-7): H03M9/00
Attorney, Agent or Firm:
Uchihara Shin