PURPOSE: To reduce the circuit scale by storing a specific data tc each flip-flop of a shift register, inputting a serial clock signal and a serial data, shifting them and detecting whether a prescribed bit number of the serial data is inputted or not.
CONSTITUTION: A shift register 2 latches a specific data from a specific data generating circuit 1 to flip-flops FF1-FFn and shifts the specific data and a serial data DT1 sequentially. A detection circuit 3 inputs a data outputted serially from the shift register 2. Whether or not the data DT1 of a prescribed bit number is inputted from the specific data included in the serial data is detected and a read end signal RE is outputted when the data of a prescribed bit number is inputted. Since the input bit number of the serial data is implemented by a simple specific data generating circuit and a detection circuit, the circuit scale is reduced.
JP3042102 | MULTIPLEXING TRANSMITTER |
JP3549756 | Block interleaved circuit |
AKIYAMA KAZUHIRO