PURPOSE: To attain transfer of accurate data even when a clock includes jitter in the interface circuit transferring data between equipments operated by two asynchronous clocks of a same frequency.

CONSTITUTION: Three stages of latches 1, 2, 3 connecting an input and an output in cascade are provided to the interface circuit and a control circuit 4 is provided to the interface circuit, which outputs a one-shot pulse when an external clock and an internal clock are inputted once. Then the latch 1 latches input data by an external clock, the latch 2 latches output data of the latch 1 by using the pulse of the control circuit 4 and the latch 3 latches output data from the latch 2 by using the internal clock. Thus, the input data are sequentially outputted from the latch 3.