Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
INTERFACE CIRCUIT
Document Type and Number:
Japanese Patent JPH0786904
Kind Code:
A
Abstract:

PURPOSE: To prevent a transistor under use from being degraded by an impressed voltage without using a transistor provided with high voltage resistance.

CONSTITUTION: An N channel MOS transistor TN 2 is used for lowering (clamping) a voltage which is higher than a power supply voltage VCC 1 and impressed from a pad P1. When inputting an H state to an input IN, a voltage boost clamp circuit U outputs a voltage at a voltage degree adding a threshold voltage Vt of this N channel MOS transistor TN 2 to the power supply voltage VCC 1 to an output OUT. On the other hand, when inputting an L state, the circuit U outputs a voltage lower than the power supply voltage VCC 1. The voltage to be impressed to the N channel MOS transistor TN 2 is made higher than the power supply voltage VCC 1 but lower than the voltage to be impressed to the pad P1, and the term of impression is short time as well.


Inventors:
KOBAYASHI KENICHIRO
Application Number:
JP22765493A
Publication Date:
March 31, 1995
Filing Date:
September 14, 1993
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
KAWASAKI STEEL CO
International Classes:
G06F3/00; H03K19/003; H03K19/0175; H03K19/0185; H03K19/0944; (IPC1-7): H03K19/003; G06F3/00; H03K19/0175; H03K19/0185; H03K19/0944
Attorney, Agent or Firm:
Satoshi Takaya (2 outside)