Title:
INTERFACE CIRCUIT
Document Type and Number:
Japanese Patent JPH1141299
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To attain the suppression of power consumption and the reduction of EMI noises by performing data transfer while making the frequency of a clock signal into 1/2. SOLUTION: The frequency of a data timing signal TM is divided into 1/2 by a flip-flop(FF) 11, and they are applied to clock terminals C of FF 31 and 32 as complementary clock signals CK and /CK. In successively inputted data DT, odd-numbered data DTO are held by the FF 31 and even-numbered data DTF are held by the FF 32 and respectively outputted. A start signal ST showing the start of the data DT is successively shifted to following steps by a shift register 20 having (n) steps of holding parts, and latch signals L1-Ln having long pulse width are outputted from the respective holding parts. Based on the latch signals L1-Ln, the odd data signal DTO and the even data signal DTE are held and outputted by respective latches 411 -41n in a data latch 40.
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Inventors:
SATO HISATAKE
Application Number:
JP19240597A
Publication Date:
February 12, 1999
Filing Date:
July 17, 1997
Export Citation:
Assignee:
OKI MICRO DESIGN MIYAZAKI KK
OKI ELECTRIC IND CO LTD
OKI ELECTRIC IND CO LTD
International Classes:
G06F7/76; H04L7/00; H04L25/40; H03K21/00; (IPC1-7): H04L25/40; H03K21/00; H04L7/00
Attorney, Agent or Firm:
Kakimoto Kyosei
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