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Patent Searching and Data


Title:
INTERFACE CIRCUIT
Document Type and Number:
Japanese Patent JPS61289724
Kind Code:
A
Abstract:

PURPOSE: To prevent disturbance from a digital signal onto an analog circuit by providing a post-stage logic circuit and a voltage division circuit sharing the power voltage with an inverter having a different switching voltage characteristic to an input section.

CONSTITUTION: A power terminal 1 is a power terminal of an input side integrated circuit 2 and 5V is applied. An input inverter consists of a depletion transistor (TR) 3 and an enhancement TR 4. The threshold voltage of the TR 4 is nearly OV and the inverting voltage of the inverter comprising the TRs 3, 4 is nearly 0.3∼0.6V. The voltage divided by resistors 5, 6 appears at an input terminal 7. The divided voltage is nearly 1V. Further, an output TR 9 of an output side integrated circuit 8 is an open drain TR and the drain is connected to an output terminal 10. Then the resistors 5, 6 are formed by polysilicon with diffusion and the internal circuit of the circuit 2 consists of TTL level logic circuits.


Inventors:
YOSHIZAWA HIROSHI
Application Number:
JP13234085A
Publication Date:
December 19, 1986
Filing Date:
June 18, 1985
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03K19/0185; H03K19/0944; (IPC1-7): H03K19/00; H03K19/094
Attorney, Agent or Firm:
Toshio Nakao