PURPOSE: To obtain the detailed data on a fault and to execute early solution of the fault by storing the wrong data obtained when an error is generated and the correct data by an interface at the data transmission side.

CONSTITUTION: The transmission data sent from an interface 10 at the data transmission side is led to the 1st driver A40 through a line group 50 and then sent to a parity check circuit 67 via the 1st timing circuit 48, etc. The parity check output of the circuit 67 is supplied to the 2nd error timing circuit 68. When an error is detected, the 1st error timing circuit 49 produces a timing pulse at a line 52 and records the transmission data to a memory A46 via the group 50. The wrong data detected at the reception side is recorded to a memory B47 from a data line group 51 via the circuit 49, etc. Thus the wrong data obtained when an error is produced and the correct data are stored to memories A46 and B47 to obtain the detailed data on a fault. This solves the fault in early time.