PURPOSE: To ensure the accurate DMA transfer by using a DREQ signal received from a control circuit as a clock input of a D-FF and as OR between an RD signal and a DACK signal received from a host system as a reset input of the D-FF respectively and then using the output of the D-FF as the DREQ signal to the host system.

CONSTITUTION: A data bus DB 13 is provided together with a direct memory access request signal lines DREQ 15 and 17, a direct memory access acknowledge signal line DACK 16, a read signal line RD 14, and a D flip-flop D-FF 20. The DREQ signal 15 sent from a control circuit 12 is used as a clock input of the D-FF 20 together with an OR secured between both signals 16 and 14 used as a reset input of the D-FF 20 and the output of the D-FF 20 used as the DREQ signal 17 to a host system 11. Thus it is possible to perform the accurate DMA transfer regardless of the processing speed of the system 11.