Title:
INTERLACE DISTURBANCE ELIMINATION DEVICE
Document Type and Number:
Japanese Patent JP3314961
Kind Code:
B2
Abstract:
PURPOSE: To eliminate picture quality disturbance while keeping interlace scanning by applying scanning conversion to an interlace scanning picture signal virtually sequentially and passing the signal through a vertical low pass filter.
CONSTITUTION: An output of a motion compensation interpolation circuit 10 and an output of an in-field interpolation circuit 14 are inputted respectively to a (1-K) coefficient device 15 and a K coefficient device 16, in which each coefficient is multiplied and outputs of the coefficient devices 15, 16 are added by an adder 17 and the circuits 15-17 form a mixing circuit 18 as a whole. Furthermore, an adder 19 adds an output signal of the adder 17 and an input signal to the device, a 1/2 coefficient device 19 multiplies 1/2 with an output of the adder 19 and the circuits 19, 20 form a vertical (low pass) filter 21 as a whole. Then motion compensation sequential scanning conversion is applied to an interlace signal virtually and the signal is fed to a vertical filter eliminating a disturbance component to eliminate interlace disturbance in both a moving picture and a still picture.
Inventors:
Taiichiro Kurita
Application Number:
JP27150792A
Publication Date:
August 19, 2002
Filing Date:
October 09, 1992
Export Citation:
Assignee:
Japan Broadcasting Corporation
International Classes:
H04N7/00; H04N7/01; (IPC1-7): H04N7/00
Attorney, Agent or Firm:
Yoshikazu Tani (1 person outside)