Title:
INTERLEAVE ADDRESS GENERATOR
Document Type and Number:
Japanese Patent JP3399904
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an interleave address generator that can relieve a processing load for generating an interleave pattern in the case of generating a Prime interleave address.
SOLUTION: A memory address generator 12 generates a memory address, a multiplier 15 reads a replacement pattern of a row corresponding to a row number, outputted from a row counter 11, from a memory 14 storing the replacement pattern to rows of a matrix, multiplies the replacement pattern of the read row with the column number of the matrix to calculate an address offset. An adder 16 reads the replacement pattern of a column corresponding to a memory address generated by the memory address generator from a memory 13 storing the replacement pattern of the column of the matrix, and sums the replacement pattern of the read column to the address offset to generate an interleave address.
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Inventors:
Tetsuya Ikeda
Hidetoshi Suzuki
Ryutaro Yamanaka
Hajime Kuriyama
Hidetoshi Suzuki
Ryutaro Yamanaka
Hajime Kuriyama
Application Number:
JP2000076879A
Publication Date:
April 28, 2003
Filing Date:
March 17, 2000
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G06F11/10; G11C8/00; G11C29/00; H03M13/27; H04B14/04; H04L1/00; (IPC1-7): H03M13/27; G06F11/10; H04B14/04; H04L1/00
Domestic Patent References:
| JP2000138596A | ||||
| JP661873A | ||||
| JP7202728A | ||||
| JP962585A | ||||
| JP11317677A | ||||
| JP2001177418A | ||||
| JP2000209103A | ||||
| JP2001102940A | ||||
| JP2001186022A | ||||
| JP8265177A | ||||
| JP1116850A | ||||
| JP634306B2 | ||||
| JP9511377A | ||||
| JP2002532939A |
Other References:
【文献】特許3257984(JP,B2)
【文献】国際公開99/25069(WO,A1)
【文献】国際公開99/25069(WO,A1)
Attorney, Agent or Firm:
Koichi Washida