Title:
INTERLEAVING DEVICE
Document Type and Number:
Japanese Patent JPH01149265
Kind Code:
A
Abstract:
PURPOSE:To allow error correction to be efficient by equipping a RAM to store address arrangement composed of a (k) sub blocks and an interleave circuit to execute specified operation. CONSTITUTION:A RAM 4 is provided to be composed of address arrangement (k)X(m)X(n) constituted of the (k) the sub blocks, in which the code word of an (m)-row (n)-column is arranged in a matrix shape on an address space. Then, an interleave control circuit 5 is also provided to write successive code word data in an oblique direction, to subtract the (m) from the row address when the row address exceeds the (m) in the sub block to be written, to repeat the moving of the address and the writing the code word data to start the writing of the code word from the other 0-th row next when an (n)-th column is achieved, to form one sub block by the (m) code words and to start a decod ing at a time point when the data of one sub block are obtained at a decoding time. Thus, after the data are written, the reading and decoding of the data in each sub block can be executed in parallel and the efficient error correction can be executed.
Inventors:
UEDA AKIRA
MURAI KATSUMI
MURAI KATSUMI
Application Number:
JP30634187A
Publication Date:
June 12, 1989
Filing Date:
December 03, 1987
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G11B20/12; (IPC1-7): G11B20/12
Domestic Patent References:
| JPS59193513A | 1984-11-02 | |||
| JPS60219880A | 1985-11-02 | |||
| JPS6129460A | 1986-02-10 | |||
| JPS58116826A | 1983-07-12 |
Attorney, Agent or Firm:
Fumio Iwahashi (2 others)