Title:
INTERLEAVING METHOD HAVING REDUNDANCY, A/D CONVERTER AND D/A CONVERTER UTILIZING THE SAME, AND TRACK HOLD CIRCUIT
Document Type and Number:
Japanese Patent JP2001308804
Kind Code:
A
Abstract:
To suppress spurious signals of electronic circuits for performing an interleave operation.
This interleaving method having redundancy for parallelly arranging a plurality of substantially same electronic circuits 101, 102 and 103 and performing an interleave operation, if the respective operating frequencies of the electronic circuits are defined as f, the number (3 in Figure 1) of the electronic circuits, which is larger than N, is arranged in parallel, to be used in order to obtain the operating frequencies (N is 2 in Figure 1) of Nf as a result of the interleave operation, and the electronic circuits 101, 102 and 103 are at least operated simulatively at random.
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Inventors:
SHIMIZU ATSUSHI
KOMURO TAKANORI
TANBA MAMORU
MUNAKATA HIDEJI
KOMURO TAKANORI
TANBA MAMORU
MUNAKATA HIDEJI
Application Number:
JP2000127104A
Publication Date:
November 02, 2001
Filing Date:
April 27, 2000
Export Citation:
Assignee:
AGILENT TECHNOLOGIES JAPAN LTD
International Classes:
H03M1/06; H03M1/66; H04B14/04; H03M1/12; (IPC1-7): H04B14/04; H03M1/12; H03M1/66
Attorney, Agent or Firm:
Okuyama Shoichi (2 outside)