Title:
INTERPOLATING CIRCUIT, GRAPHIC CONTROLLER CIRCUIT, COMPRESSED PIXEL DATA GENERATING CIRCUIT, COMPRESSED PIXEL DATA EXPANDING CIRCUIT, COMPUTER SYSTEM, SCALING-UP METHOD, AND COMPRESSED PIXEL DATA GENERATING METHOD
Document Type and Number:
Japanese Patent JP3167631
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To generate accurate pixel data which are scaled up or downsized by providing an interpolator which generates additional pixel data and an overwriting circuit which makes the interpolator generate additional pixel data from adjacent pixel data.
SOLUTION: The interpolator 490 can generate additional pixel data by interpolating source video pixel on a current scan line with pixel data received through a line buffer output bus 398. A multiplexer 485 normally outputs pixel data on a previous scan line to an output bus 498, so the interpolator 490 generates additional pixel data from pixel data on the previous scan line. If, however, a slope overload state is present, the interpolator 490 can use ≥1 adjacent pixel data instead of the pixel data on the current scan line.
Inventors:
Alexander Jay Egrit
Application Number:
JP31238696A
Publication Date:
May 21, 2001
Filing Date:
November 22, 1996
Export Citation:
Assignee:
Cirrus Logic,Inc.
International Classes:
G06T3/40; G09G5/36; G09G5/00; (IPC1-7): G09G5/36; G06T3/40; G09G5/00
Domestic Patent References:
| JP5284485A | ||||
| JP746412A | ||||
| JP594521A | ||||
| JP6189786A | ||||
| JP2131038A | ||||
| JP3265370A | ||||
| JP502413A | ||||
| JP2129766A | ||||
| JP5084123A | ||||
| JP3112283A |
Attorney, Agent or Firm:
Shusaku Yamamoto