PURPOSE: To transfer a large amount of data at a high speed with high efficiency, by connecting separatably specific processors together through dedicated local buses, providing a data transfer buffer between the local buses, and empolying DMA transfer together.

CONSTITUTION: When data is transferred from the 1st local memory 43 to the 2nd local memory 53 the 2nd processor 52 actuates a DMA controller 56 to inhibit the local buses from being used by the 1st and the 2nd processors 42 and 52. A bus connection control circuit 42 actuates an address bus driver 20 to connect address parts of the 1st and the 2nd local buses 44 and 45 together and also to connect a two-way data bus driver receiver 21 in such a direction the data transfer from the 1st local bus 44 to a data transfer buffer 25 is permitted. After the data transfer, the DMA controller 56 disconnect the address parts of the 1st and the 2nd local buses from each other and local data processing is carried out.