複数スレッドの同時実行に対応するコンピュータシステムにおける割込み処理の方法

Title:

複数スレッドの同時実行に対応するコンピュータシステムにおける割込み処理の方法

Document Type and Number:

Japanese Patent JP2005502119

Kind Code:

A

Abstract:

The present invention provides a mechanism for handling interrupts on a processor that supports multiple-threads concurrently. The processor's resources are allocated to provide multiple logical processors. In response to a common interrupt, the logical processors vie for access to a shared register. The first logical processor to access the shared register handles the common interrupt. The remaining logical processors return from the interrupt.

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Inventors:

Bob Holtz, Scott
Marty, Keshabram

Application Number:

JP2003525460A

Publication Date:

January 20, 2005

Filing Date:

August 01, 2002

Export Citation:

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Assignee:

Intel Corporation

International Classes:

G06F9/46; G06F9/00; G06F9/48; G06F13/24; G06F; (IPC1-7): G06F9/46

Attorney, Agent or Firm:

Tadahiko Ito
Shinsuke Onuki
Tadashige Ito

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