PURPOSE: To unnecessitate the converting circuit to a branching destination address by outputting the branching destination address onto an address bus in which a micro-processor is coupled directly from an interrupting module side and transferring it to the micro-processor.

CONSTITUTION: An interrupter INT transfers an interruption request signal inversion IRQ to a micro-processor CPU. From the CPU, interruption response signal inversion ITAC and address strobe signal inversion AS are sent to INT as a response. At the INT, an interruption factor signal ACT and an interruption address table INTA are sent. An interruption address ADR read by the INTA is supplied to an interruption address preparing circuit INTAG. At the INTAG, a timing signal CNT supplied from the INT is received, synchronized to it and the above-mentioned interruption address ADR is sent to an address bus ADB.