PURPOSE: To generate plural necessary interruption addresses in order by generating one interruption signal, by utilizing a delay effect of a shift register, in an interruption address generating circuit of a sequencer.

CONSTITUTION: In a sequencer by which processing is executed in accordance with an address generated from a program counter 1, when an interruption signal B is generated, this signal is latched by a latching circuit 7, and a flip-flop circuit 4 inhibits supply of a clock A to the program counter 1. Flip-flop circuits 5, 6 constitute a 2 bit shift register for delaying an output, and by these outputs D, E, two address (x) and address (y) which are desired to be processed by means of interruption by a selecting circuit 2 are selected and outputted in order.