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Patent Searching and Data


Title:
INTERRUPTION CONTROLLER
Document Type and Number:
Japanese Patent JPS5734255
Kind Code:
A
Abstract:

PURPOSE: To reduce program examination time by storing a program address register and an address status to a corresponding shunting register with "interrupted effective mark" for shunting of said register and status at the time interrupted.

CONSTITUTION: Now in a case where a program is executed in a level 3, when an interruption of a level 1 is generated, contents of a program address PA register 3 and a program status PS register 4 are stared by an interruption controlling circuit 2 in the corresponding registers. In the case an effective mark indicating that the level 3 is interrupted is attached to a shunting register. Then, starts PA, PS of the level 1 are extracted from a column corresponding to the level 1 in an interruption table 5, and are stored in the registers 3, 4 respectively to execute the program of the level 1. Further, also in a case of return, with use of "interruped effective register", return is performed rapidly.


Inventors:
FUKUDA HIROSHI
Application Number:
JP10968080A
Publication Date:
February 24, 1982
Filing Date:
August 07, 1980
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G06F11/00; G06F9/06; G06F9/46; G06F9/48; (IPC1-7): G06F9/06; G06F9/46; G06F11/00