Title:
INVERSE TRANSPORT PROCESSOR WITH MEMORY ADDRESS CIRCUIT
Document Type and Number:
Japanese Patent JPH07297855
Kind Code:
A
Abstract:
PURPOSE: To provide an inverse transport processor system for a TDM packet signal TV receiver. CONSTITUTION: When a related memory address is inputted to a memory address input port by an address multiplexer 17, data generated by respective component payload and microprocessor are stored in the respective blocks of a common buffer memory. A decrypting device 16 is provided and in accordance with a decrypting key characteristic for a packet, payload data are decrypted. A detector 15 detects the payload, including authenticity data. A memory data output port is linked to a bus each mutually connected with program component processors 21-24. The loss of incoming program data is prevented, and it is ensured that all the component processors receive services.
Inventors:
KEBIN ERIOTSUTO BURITSUJIUOOTA
MAIKERU SUKOTSUTO DEIISU
MAIKERU SUKOTSUTO DEIISU
Application Number:
JP9722095A
Publication Date:
November 10, 1995
Filing Date:
April 21, 1995
Export Citation:
Assignee:
THOMSON CONSUMER ELECTRONICS
International Classes:
H04N7/08; G06F15/00; H04N5/00; H04N7/081; H04N7/16; H04N7/30; (IPC1-7): H04L12/56; H04N7/169; H04N7/30
Attorney, Agent or Firm:
Yoshikazu Tani (1 person outside)