Title:
INVERTER APPARATUS
Document Type and Number:
Japanese Patent JP3680561
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the consumption current of a control portion and reduce the variation width of a delay time and intend a cost down, in an inverter apparatus wherein the power of its load can be controlled by an externally fed PWM signal having a variable duty factor.
SOLUTION: In an inverter apparatus having an inverter circuit 2 for feeding a high-frequency power to a load 1, an inverter controlling circuit 3 for controlling the inverter circuit 2, and a PWM-signal transferring circuit 4 for receiving a PWM signal with a variable duty factor and transferring it to the inverter controlling circuit 3 wherein the output frequency given from the inverter controlling circuit 3 to the inverter circuit 2 is varied responding to the output fed from the PWM-signal transferring circuit 4 to control the power fed from the inverter circuit 2 to the load 1, a correcting means for correcting the transferring delay time of the PWM-signal transferring circuit 4 is added to the apparatus.
Inventors:
Yoshikazu Kado
Katsumi Sato
Katsumi Sato
Application Number:
JP17910998A
Publication Date:
August 10, 2005
Filing Date:
June 25, 1998
Export Citation:
Assignee:
MATSUSHITA ELECTRIC WORKS,LTD.
International Classes:
H05B41/24; H02M1/08; H02M7/48; H05B41/392; (IPC1-7): H02M7/48; H02M1/08; H05B41/24; H05B41/392
Domestic Patent References:
| JP9185997A | ||||
| JP2273080A | ||||
| JP7259791A |
Attorney, Agent or Firm:
Masahiko Kurata
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