PURPOSE: To reduce power consumption by connecting input terminals of 2nd and 3rd inverters(INV) to the output terminal of a 1st inverter, and connecting output terminals of the 2nd and 3rd INV to the gate of a complementary transistor(TR).

CONSTITUTION: When an input voltage level changes from an L to an H and the output of an INV 1 passes through the switching level of an INV 2, the output level of the INV 2 changes from an L to an H level. A P-channel TR P1 of an output stage changes from ON to OFF and a final output goes from an H level to a high impedance and no through-current flows to the TRs P1, N1. When the output of the INV 1 passes a time reaching the switching level of an INV 3, the output level of the INV 3 changes from an L to an H level, the TR N1 is turned on and a final output goes to an L level. When the input level changes from an H to an L, the final output changes to H → high impedance → L. Since the TRs P1, N1 are not simultaneously turned on, no through- current flows to the output stage and the power consumption is reduced.