To provide an inverter circuit configured such that narrowing of a width of a maximum amplitude of output is reducible.

One source/drain region of a first transistor is connected to one source/drain region of a second transistor, the other source/drain region of the second transistor to one voltage supply line, the gate electrode to one source/drain region of a third transistor, the gate electrode of the third transistor to the other source/drain region, and the other source/drain region of the third transistor to one voltage supply line. One source/drain region of a fourth transistor is connected to a node portion to which the gate electrode of the second transistor and one source/drain region of the third transistor are connected, and other source/drain regions of the first transistor and fourth transistor are connected to the other voltage supply line. Then an input signal is applied to the gate electrode of the first transistor and the gate electrode of the fourth transistor.