Title:
INVOLATILE SEMICONDUCTOR STORAGE DEVICE AND ITS DRIVING METHOD
Document Type and Number:
Japanese Patent JP3675898
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the variance of threshold voltage in a flash memory.
SOLUTION: Wells are separated per datelines b1 to bm by using an SOI structure or embedding element separation structure. Switching transistors MW1 to MWm are provided between respective sources for memory cells M11 to M1n, M21 to M2n, and Mm1 to Mmn wherein the wells are separated every data line and data lines, and the sources and substrate are connected with each other on the memory cell side of the selection switch. Therefore, a well voltage can be set every data line and it becomes possible to examine the deletion side and writing side every bit, resulting in less variance of threshold voltage.
Inventors:
Takayuki Kawahara
Takashi Kobayashi
Katsutaka Kimura
Takashi Kobayashi
Katsutaka Kimura
Application Number:
JP20200095A
Publication Date:
July 27, 2005
Filing Date:
August 08, 1995
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H01L21/8247; H01L27/10; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP4352362A | ||||
| JP6005870A | ||||
| JP61046058A | ||||
| JP7142618A |
Attorney, Agent or Firm:
Katsuo Ogawa
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