Title:
局地化されたシリコンエピタキシャルシード形成によるバルクウェハにおける隔離された半導体層
Document Type and Number:
Japanese Patent JP7137538
Kind Code:
B2
Abstract:
An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral surfaces of the substrate at the buried isolation layer are covered with a dielectric sidewall. A seed trench is formed through the buried isolation layer to expose the substrate. A single-crystal silicon-based seed layer is formed through the seed trench, extending above the top surface of the buried isolation layer. A silicon-based non-crystalline layer is formed contacting the seed layer. A cap layer is formed over the non-crystalline layer. A radiant-induced recrystallization process converts the non-crystalline layer to a single-crystal layer aligned with the seed layer. The cap layer is removed and the single-crystal layer is planarized, leaving an isolated semiconductor layer over the buried isolation layer.
Inventors:
Daniel Nelson Carrosers
Jeffery Earl Debor
Jeffery Earl Debor
Application Number:
JP2019143488A
Publication Date:
September 14, 2022
Filing Date:
August 05, 2019
Export Citation:
Assignee:
Texas Instruments Incorporated
International Classes:
H01L21/20; H01L21/02; H01L21/76; H01L27/12
Domestic Patent References:
| JP59004048A | ||||
| JP2081422A |
Foreign References:
| US20070281446 | ||||
| US20080274594 |
Attorney, Agent or Firm:
Hitoshi Sato
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