PURPOSE: To reduce the occupied area on a chip, to reduce power consumption and to improve the operating speed by forming a state transition circuit through the use of a latch circuit having nearly a half number of D flip-flops or over.

CONSTITUTION: The counter is provided with a state transition circuit in which even stage numbers (4-stage) of latch circuits 51-54 are connected in cascade. That is, a noninverting output terminal Q of the latch circuit 51 and a data input terminal D of the latch circuit 52 are connected, and then the latch circuits 52, 53 are configured similarly. Then a noninverting output terminal Q of the latch circuit 54 and the data input terminal D of the latch circuit 51 are connected to form a 4-stage state transition circuit. Furthermore, an inverting output terminal QX of the latch circuit 54 is connected to the data input terminal D of the latch circuit 51. A wiring for the supply of a clock signal CLK is connected in common to each clock input terminal CK of the latch circuits 51-54. Moreover, outputs of the Johnson counter are outputs A1-A8 of AND gates 41-48 as a decode circuit.