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Title:
JOINTING METHOD OF SILICON WAFERS
Document Type and Number:
Japanese Patent JP2001155977
Kind Code:
A
Abstract:

To provide a jointing method of silicon wafers, which pauses no risk of without flaking at jointing interface, by preventing voids when silicon substrates are jointed.

When a first silicon substrate 1 having a circuit element 3 formed thereon and a second silicon substrate 11 as a base stage are overlapped and jointed, a diffusion preventive layer 4 made of a metal thin film containing at least one of Ni, Cr, W and Al for preventing diffusion of Au is formed on the first silicon substrate 1. An Au layer 5 is formed thereon. An Sn layer 13 is formed on the second silicon substrate 11. The Au layer 5 of the first silicon substrate 1, the Sn layer 13 of the second silicon substrate 11 are overlapped and a prescribed load is applied thereto at temperatures of 300 to 400°C to joint the silicon substrates 1 and 11 through alloy junction.


Inventors:
SAITO HIROSHI
AKAI SUMIO
KATAOKA KAZUSHI
Application Number:
JP33548099A
Publication Date:
June 08, 2001
Filing Date:
November 26, 1999
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC WORKS LTD
International Classes:
B81C3/00; G01L9/00; G01L9/04; G01P15/12; H01L21/02; H01L21/52; H01L41/08; (IPC1-7): H01L21/02; B81C3/00; G01L9/04; G01P15/12; H01L21/52; H01L41/08
Attorney, Agent or Firm:
Junji Ando (1 person outside)