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Title:
JUNCTION BREAK-DOWN TYPE PROGRAMMABLE READ-ONLY MEMORY SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5521114
Kind Code:
A
Abstract:

PURPOSE: To achieve writing in a short time by applying a collective current to a P+ region formed in a part of an emitter-base junction.

CONSTITUTION: When a writing pulse may be applied to the intermediate line between an emitter electrode E of a selected memory cell and a word line current absorption terminal C so that the junction face between an emitter region 17 and base region 14 is biased reversely, almost of the writing current is directed to a collector region 13 and N+-type buried layer 12 through a P+region adjacent to the emitter region 17. Therefore, the writing can be established by breaking down the P-N junction of the contact portion between the emitter region 17 and P+ 15. In this case, because the area of the contact portion of the emitter region 17 with the P+ region 15 can be reduced, the collection of the current is easily caused and a break-down is frequently occurred.


Inventors:
OONO NOBUHIKO
TAKEDA TADAO
Application Number:
JP9358578A
Publication Date:
February 15, 1980
Filing Date:
August 02, 1978
Export Citation:
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Assignee:
HITACHI LTD
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G11C17/06; G11C17/14; H01L21/8229; H01L27/102; (IPC1-7): G11C17/00; H01L27/10



 
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