Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3112047
Kind Code:
B2
Abstract:
PURPOSE: To reduce current consumption at a waiting time in a semiconductor integrated circuit using plural CMOS circuits using a minute MOS transistor.
CONSTITUTION: The device parameter of S1 is set so that the leakage current of a switching transistor S1 constituting a power supply switch being turned off at a waiting time is smaller than the total sum of the sub threshold current of the MOS of the (p) channel or the (n) channel in an off-state of plural CMOS circuits Ci. Thus, the current at a waiting time of plural CMOS circuits Ci becomes the small leakage current of the switching transistor S1 not but the large sub threshold current of the Ci in the case of using the minute MOS.
Inventors:
Takayuki Kawahara
Yoshiki Kawajiri
Takesada Akiba
Masashi Horiguchi
Takao Watanabe
Kikkawa Goro
Yasushi Kawase
Toshikazu Tachibana
Masakazu Aoki
Yoshiki Kawajiri
Takesada Akiba
Masashi Horiguchi
Takao Watanabe
Kikkawa Goro
Yasushi Kawase
Toshikazu Tachibana
Masakazu Aoki
Application Number:
JP29479992A
Publication Date:
November 27, 2000
Filing Date:
November 04, 1992
Export Citation:
Assignee:
株式会社日立製作所
日立デバイスエンジニアリング株式会社
日立デバイスエンジニアリング株式会社
International Classes:
G06F1/32; G11C11/405; G11C11/407; G11C11/418; H01L27/10; H03K19/0948; (IPC1-7): G11C11/407; G11C11/418; H01L27/10; H03K19/0948
Domestic Patent References:
| JP629834A | ||||
| JP5110392A | ||||
| JP5268065A |
Other References:
日経マイクロデバイス（１９９３−３）Ｐ．４８−５１
Attorney, Agent or Firm:
Yasuo Sakuta
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