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Title:
半導体パッケージの積層組立体
Document Type and Number:
Japanese Patent JP4829869
Kind Code:
B2
Abstract:

To provide a stacked assembly of semiconductor packages, in which the adhesion at high temperatures and the solder joint area of leads are increased to enhance the impact durability.

A stacked assembly of semiconductor packages comprises a first semiconductor package 210 and at least one second semiconductor package 220. The first semiconductor package 210 comprises at least a first chip 211, multiple first outer leads 212 of a leadframe, and a first encapsulant 213. The second semiconductor package 220, which is mounted onto the first semiconductor package 210, comprises at least a second chip 221, two or more second outer leads 222 of a leadframe, and a second encapsulant 223. The second outer leads 222 are exposed on the outside of the second encapsulant 223. At least each second outer lead 222 has a U-shaped recessed cut end surface which is solder-joined to the joint of the corresponding first outer lead 212.

COPYRIGHT: (C)2009,JPO&INPIT


Inventors:
Fusumasa
Application Number:
JP2007299132A
Publication Date:
December 07, 2011
Filing Date:
November 19, 2007
Export Citation:
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Assignee:
Strength Science & Technology Co., Ltd.
International Classes:
H01L25/10; H01L23/50; H01L25/11; H01L25/18
Domestic Patent References:
JP7147379A
JP62047147U
JP10041455A
Attorney, Agent or Firm:
Masaki Hattori



 
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