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Patent Searching and Data


Title:
LAMINATED CHIP COMPONENT AND METHOD FOR MANUFACTURING THEREOF
Document Type and Number:
Japanese Patent JP2001093732
Kind Code:
A
Abstract:

To prevent a disconnections in a through hole due to the difference in shrinkage ratio between a conductor pattern and an insulating sheet at baking and to prevent disconnections between a coil and a capacitor due to the difference in the shrinkage ratio and the difference in reactivity between two kinds of conductor patterns.

An insulating sheet, where a conductor is formed is laminated on the top surface of a conductor pattern at a position facing a through-hole. Then the through hole is filled with a conductor to connect the conductor pattern of an upper layer and the pattern of a lower layer to each other. Consequently, a conductive material can be supplied from the conductor formed on the top surface of the conductor pattern into the through-hole, so no disconnection is made in the through-hole.


Inventors:
MURAMATSU NOBUAKI
OGAWA TAKAHIRO
Application Number:
JP26985699A
Publication Date:
April 06, 2001
Filing Date:
September 24, 1999
Export Citation:
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Assignee:
TOKO INC
International Classes:
H01F41/04; H01F17/00; H01G4/40; H03H1/00; H03H7/01; H05K1/11; (IPC1-7): H01F17/00; H01F41/04; H01G4/40; H05K1/11
Attorney, Agent or Firm:
Yu Ota