To provide a laminated chip varistor having small deterioration in varistor characteristics, even when the surface of an external electrode is further plated, and to provide its manufacturing method.
A laminated chip varistor 1 is provided with a varistor element assembly 1, having a plurality of varistor layers 1a, 1b, and 1c and internal electrodes 2a and 2b, arranged so as to sandwich each varistor layer, external electrodes 3a that are formed at the end part of this varistor element assembly 1 and that are connected with the internal electrodes, and glass layers 4 formed between the varistor element assembly 1 and the external electrodes 3a. Moreover, a plating layer 3b and a plating layer 3c are formed on the surface of the external electrode 3a.
HIROSE OSAMU
OCHIAI TOSHIAKI
Shiro Terasaki
Toyotaka Abe